The invention relates a package method, and in particular to a wafer stacking package method.
In flip chip interconnect technology FC, pads are disposed on active surfaces of chips, and bumps are formed on the pads. Subsequent to the flip of a chip, the bumps are respectively connected to contacts of carriers, thus, internal circuits of carriers can be electrically connected to external electronics. Due to the applicability with high pin contact, small package area and short signal transferring path, flip chip interconnect technology is widely used. Typically, flip chip interconnect technology comprises flip chip ball grid array, FCBGA and flip chip pin grid array, FCPGA.
FIG. 1˜FIG. 6 are cross sections of conventional flip chip ball grid array structures. Referring to FIG. 1, a thinned wafer 21 is provided, and an adhesive paste 22 is coated on backside thereof. As shown in FIG. 2, a wafer supporter 30 is provided for supporting the wafer 21, thus, the wafer 21 can be cut into chips 29. Referring to FIG. 3, a die 29 with the adhesive paste 22 thereon is taken out to be put on a predetermined area 40 of a substrate 60, as shown in FIG. 4, this chip can be referred to as a principal chip 31. Referring to FIG. 5, another chip 41, auxiliary chip, is taken out to be put on the principal chip for attachment using the adhesive paste 22. The principal and auxiliary chips 31 and 41 are wire 55 bonded to achieve a package, as shown in FIG. 6.